DEVICES FOR MULTIPLYING MODULO NUMBERS WITH ANALYSIS OF THE LOWER BITS OF THE MULTIPLIER

Авторы

  • S. Tynymbayev Almaty university of Power Engineering and Telecommunication, Almaty, Kazakhstan
  • R. Sh. Berdibayev Almaty university of Power Engineering and Telecommunication, Almaty, Kazakhstan
  • T. Omar Almaty university of Power Engineering and Telecommunication, Almaty, Kazakhstan
  • S. A. Gnatyuk National aviation university, Kyiv, Ukraine
  • T. A. Namazbayev al-Farabi Kazakh national university, Almaty, Kazakhstan
  • S. Adilbekkyzy Almaty university of Power Engineering and Telecommunication, Almaty, Kazakhstan

Ключевые слова:

public-key cryptosystem, hardware encryption, modular multiplication, remainder former.

Аннотация

Various approaches of modulo multiplying multi-bit (large) numbers in modulus are considered. An
algorithm for multiplying numbers is given, where the modular multiplication process is divided into steps, and in
each step, by combining the multiplication operations of the previous partial remainder by two with the operation of
reducing the multiplication results modulo, partial remainders is formed. The circuit diagrams of multipliers of
numbers modulo with the analysis of the lower bits of the multiplier with the sequential and matrix formation of remainders
are considered. The proposed modulo multipliers do not require pre-calculations and all calculations do not
go beyond the bit grid of the module.

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Опубликован

2019-07-19

Как цитировать

S. Tynymbayev, R. Sh. Berdibayev, T. Omar, S. A. Gnatyuk, T. A. Namazbayev, & S. Adilbekkyzy. (2019). DEVICES FOR MULTIPLYING MODULO NUMBERS WITH ANALYSIS OF THE LOWER BITS OF THE MULTIPLIER. «Вестник НАН РК», (4), 38–45. извлечено от http://91834.libg.asia/bulletin-science/article/view/1482

Выпуск

№ 4 (2019): ВЕСТНИК НАЦИОНАЛЬНОЙ АКАДЕМИИ НАУК РЕСПУБЛИКИ КАЗАХСТАН

Раздел

Статьи